Latest Ideas for Algorithm Implementation
Links to Manchester Specification pages
Analogue card
Service module
Crate Layout
VME Interface
Most of the rest of this page is by now obsolete. Full specifications
of the algorithm can be found from the
FTT documents page.
Following Dortmund Meeting (25/9)
Diagram summarising latest plans for algorithm placement on FPGA
ps
pdf
From Birmingham Meeting (14/6)
Andre's latest proposal for merging FEM track segment outputs
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pdf
From Birmingham Meeting (9/5)
Andre's block diagram of L1 algorithm now generalised for PRE L1KEEP
eps
pdf
Some of Andre's transparencies
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pdf
From Video Conference (5/4)
Scans of Andre's hand written transparencies:
Front End Module Block Diagram
eps
pdf
Timing estimates for each L1 function
eps
pdf
Possible scheme for implementing L1 segment finding AFTER L1 keep
ps
pdf
Possible crate layout from Adam
pdf
Andre's plots on change in (kappa / phi) coordinate with timeslice
for all track segments
ps
pdf
- Shown is Delta Kappa (in GeV-1) and Delta Phi
(in radians) versus timeslice at 20 MHz. The four plots in each case are
the four separate trigger layers.
Level 1 Trigger Module I/O Ideas from Andre (27/3)
Explanatory text
Design 1: Encoded data transfer
ps
pdf
Design 2: Unencoded data transfer (LVDS)
ps
pdf
Design 3: Unencoded data transfer (Optical link)
ps
pdf
Updated Block diagrams from Adam and Dave S (28/3).
System overview
pdf
Front End Module overview
pdf
Qt algorithm
pdf
Segment Finding algorithm
pdf
Level 1 trigger
pdf
Old (and mostly obsolete) stuff
Note on first ideas on Front End Module / Block diagrams
ps
pdf
Block diagram (Richard) of CAM - RAM interaction in extracting (kappa-phi)
information from shift registers.
gif
eps
Explanatory text
Web search on CAMs (Dave M)
Introduction to what CAMs do (from UTCAM)
pdf
List of relevant web sites
Last update 11/05/00