I/O Upper Limits for L1 Triggering ================================== Basic assumptions: drive technologies to the limits and make L1 trigger decision on one card. The last assumption is motivated by the fact that a track segment measured in one trigger group has to be matched with track segments from other groups in up to 5-6 neighbouring cells. A predefined sorting algorithm would have to decide to which linker card a segment has to be sent. The number of connections between cards has to be increased. Data Transfer: I consider LVDS and optical link. For the optical link I assume a data transfer rate of 1.6 Gbyte per link and assume that 30 links fit (including demux) onto a single board. For LVDS a clock rate of 100 MHz is assumed what should work if distances between cards are not too long. Linker Card: I assume that up to 500 lines at a frequency of 100MHz can be realized on a single board. that poses an upper limit on the input rate of the FPGA of about 6Gbyte/s. Designs: I considered three designs: 1. LVDS transfering track segments encoded 2. LVDS transfering track segments unencoded 3. Optical Link transfering track segments unencoded 1. LVDS transfering track segments encoded (fig.1) ================================================== Because 30 LVDS connectors cannot be put onto a single board merger cards have to be used which introduce some delay. Equivalent to the L2 design 5 merger cards are used each having 6 inputs links. CJC1 merger cards have two outputs, CJC2 merger have one. A histogram 60x10 (kappa,phi) is assumed to trigger tracks down to 100MeV transverse momentum. At the merger cards 9 bits per track segment (1t0, 4phi, 4 kappa) have to be received from the FEM. Track segments are assumed to be valid only 1BC in the same bin. If not the track has to be sent again for the following BC. 5 tracks can be sent simultenously resulting in a maximum transfer rate of 50 tracks per BC per FEM. Because after merging the histogram is bigger one more bit is needed for the track segment representation (actually 2 more bits are needed but the second bit is hardware coded by the link). 8 links go from the merger card to the L1 Linker card through which 48 track segments can be transfered (96 per trigger group). Because merger card and L1 linker card are connected by 8 links 480 lines have to be put on the L1 linker board with 100MHz clock. The limited number of track segments will cause inefficiencies in jet-like events and in events with high track multiplicities. The limitation can be partially overcome by transmitting tracks ordered in transverse momentum. For low multiplicity events like VM production no shortcomes are expected. 2. LVDS transfering track segments unencoded (fig.2) ==================================================== Similar to the previous design 5 Merger cards are needed but the information to be sent is different. Histograms or phi sectors of histograms are sent where each bin can have three states: no track segment, t0 validated track segment (only 1BC valid), non-t0 validated track segment. The main restriction comes again from the link between the merger card and the L1 linker card. The size of the histogram can be as large as 60x10 (phi,kappa). That allows track triggering down to 160 MeV transverse momentum. Between the FEM and the merger card 1/6th of the histogram (10x10) is transmitted. Per link between merger cards and the L1 linker card half of the histogram is transmitted. It is assumed that the tristates can be efficiently coded and decoded. If that is not feasible the histogram has to be reduced to 60x8. Concerning track segment multiplicities that design has no upper limit. Because the data transfer rate between FEM and merer card is not so large a transfer rate between 40-100MHz can be chosen. By using the fastest rate the transfer can be finished after 40ns. These scheme has no limitation in the maximum number of track segments. 3. Optical Link transfering track segments unencoded (fig.3) ============================================================ This design is similar to the previous one but does not have an additional delay due to merger cards. 30 links go directly from the FEMs to the L1 linker card. Each FEM sends a 10x10 sized histogram with each bin represented by a tristate. Challenging is the assembling of 30 optical links and their demultiplexer on a single board. The L1 linker board and its 480 data lines has to be operated at 100MHz. The transverse momentum is limited to above 160MeV but there is no limitation in the maximum track segment multiplicity. Conclusion ========== The decision between using a encoded transfer or unencoded transfer of track segments sould be answered by the algorithms to be used on the FEM and on the L1 linker board. For the track segment linking a histogram representation seems to be advantageous. On the FEM the question is still open. If timing cosiderations show that the additional delay due to merger cards makes the L1 trigger impossible the usage of an optical link has to be considered. Standard optical links fitting our requirements should be available on the market.