T0 inputs: TIMING CHANGED today morning, 10.7.2009

The phase of 0T0C signal was measured: it is now 0 (before it was 7). I.e. all the other inputs are now shifted be 7 to the left. 0T0C edge is NEGATIVE now -it was set manually in CTP + correction in CTP database was done (i.e. l0inputdb->save and switched ->save)

T0 trigger input board (module1), 26.5.2009

T0 DIM server was used to control the signal sent to CTP L0 inputs. All the inputs signals (toggling, signature, random, normal) were measured with snapshot memory, and gave results as expected. This should be repeated for spare module2 (end of June or later). In July, FPGA is going to be updated, so it should be tested again.

signal DIMchannel/strobing edge CTPin signature
0T0C 1 9 70
alt positive
0TVX 3 10 72
alt positive
0T0A 2 11 71
alt negative
0TSC 4 12 73
alt negative
0TCE 5 17 74
alt positive

Note about 0T0A (see previous revison from 2008: the patch cable 16 connected between
Rack25/Patch panel/bottom/B/17 and CTPSwitch Rx-41 input is damaged
: seems cable is OK -i.e. repaired by itself (toggling signature phase measurement is fine.

Topic attachments
I Attachment Action Size Date Who Comment
pngpng 0t0a.png manage 1.3 K 26 May 2009 - 14:30 AntonJusko  
pngpng 0t0c.png manage 1.2 K 26 May 2009 - 14:27 AntonJusko  
pngpng 0tce.png manage 1.2 K 26 May 2009 - 14:31 AntonJusko  
pngpng 0tsc.png manage 1.2 K 26 May 2009 - 14:31 AntonJusko  
pngpng 0tvx.png manage 1.2 K 26 May 2009 - 14:32 AntonJusko  
Topic revision: r5 - 10 Jul 2009 - 08:58:52 - AntonJusko
 
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