Minutes 21/03/00 (Birmingham)
Present: A. Baird, J. Dowell (in part), Y. Fleming,
D. Mercer, P. Newman, D. Sankey, A. Schoening, R. Staley
Minutes of this meeting consist of postscript files of talks (where
available), some pointers to other bits of information and a few notes.
Update on L2 / L3 (A. Schoening)
Andre' summarised the latest situation with the level 2 and 3 systems and
with the overall project. Some points that are worth noting from Andre's
talk and the surrounding discussion
- SCS have now produced a final costing for the L2 system (the feasibility
study can be found from
here ). - The costs were a little
more than expected. However, with David Mueller paid by ETH Zuerich to work
for 2 years at SCS, the overall costs become 235k SwF for hardware and
400k SwF for manpower. This matches the figures in the FTT proposal, though
not all moneys have yet been obtained from funding bodies.
- A first plan now exists for level 3. Details (from a talk by Jurgen
Naumann) can be found here as
The planned LVDS daisy-chain caused some discussion.
- Andre' has investigated the possibility of adding FPGAs at level 2
to make fast decisions based on the (pre-DSP?) list of tracks. A first
attempt at simulating an invariant mass combination showed that we have time
for 1000 mass combinations with one APEX 20k400. - This would be enough
to search for D* in events with <~ 30 tracks. It would certainly be
enough to make e.g. pt sums.
More investigations of the
precision obtained etc are needed.
- A reminder!... As things stand, we plan to keep the DCr-phi trigger in
place, even when we have a L1 FTT trigger. This has implications for the
design of the plug-through card.
- The level 2 and 3 groups are aiming to deliver prototypes for October
2000, which is a lot earlier than the present L1 prototype aim. - The
question is what (if anything) can we provide in time for October?
Level 1 Front End
Most of the meeting was taken up with discussion of the algorithm and
how it could be realised in hardware.
The most recent block diagrams from Adam / Dave
were shown. These can be
and will be updated soon.
Adam is presently assuming that the ADC card expects
8-bit input at 80 MHz.
A final decision is needed on whether to use encoded (with load balancing)
or unencoded mode CAMs or just simple Look Up Tables.
Andre' gave considerable detail
on his own level 1 ideas. His talk is here as
For reference, an earlier talk by Andre on level 1 (October 99) can be found
This contains lots of info on where to place pivot layers etc. Also
note from here the result that the phi and
kappa coordinates associated with a valid track segment change within the
period of validity even at 20 MHz synchronisation frequency
Unless anyone objects quickly, the following will soon become a `decision'!..
- In contrast to earlier minutes, we now plan to
include all four trigger
groups in the L1 trigger. (including the CJC2
layers). This will be essential from an efficiency /redundancy point of view
and will help us ensure that essentially the same conditions are required
at L1 and L2 (thereby making efficiency calculations etc much easier).
This has serious implications for the layout of the crates / moving around
of the data. Some block diagrams (Andre') showing how the data could be
moved into the L1 trigger can be found under `Level 1 Triggering I/O ....'
Proposal to use ASIC Readout Receiver Chip
Another interesting possibility was raised by Andre'.... -
An ASIC has been proposed
by a company founded by Thom Wolff (DCr-phi trigger designer). This
ASIC would essentially replace the FADCs and the Q-t
extraction (including the z-coordinate).
A few details can no longer be found
here (removed at request of Thom Wolff).
Clearly such a custom chip could simplify the L1 design considerably.
However, several important questions and possible objections were raised
(Adam etc). - Most importantly, the flexibility and reprogramming
possibilities of the currently proposed FPGA solution are lost. Can e.g.
recalibrations be easily done? There
are also doubts about whether it is physically possible to pass
the many signals from all necessary CJC channels into the ASICs.
To help us understand the proposed ASIC better and to assess whether it
will work for our purposes, it is propoed to
invite Thom Wolff to one of the next FTT meetings
(5th April video
conference or 9th May in B'ham, probably 5/4).
Level 1 Trigger
The kappa-phi matching between different layers was discussed at length.
Some collected thoughts of relevance to the design of the L1 trigger
- The kappa-phi region covered by a single CJC region has a very strange
shape in kappa-phi space when phi is measured from the vertex. When phi
is measured from the apex, the kappa-phi space is rectangular.
- At (16 x 60) kappa x phi granularity, 1 CJC cell corresponds to two
phi bins (i.e. one either side of the wire).
- In the general case, there is a `phase shift' in the phi bins between
different layers. - Unfortunately they do not line up neatly, so account will
have to be taken of this when defining histograms for linking.
- As mentioned above, the kappa-phi positions of a valid segment change
from bunch crossing to bunch crossing.
Pivot Layer Studies (Y. Fleming)
Yves has been thinking about the question of how best to exploit the
pivot layer technique. He has code working which takes a given pattern
in the shift registers (including the case where cell boundaries are crossed),
decides whether the pattern is valid (using FTTEMU), then
propagates that pattern to the point where the pivot element is struck to
check the pattern is not lost (e.g. because one of the hits has clocked
off the register, or else has not yet appeared because the drift
distance is long).
This code is now being used to assess where to place the pivot element and
how long the register should be. The proposed means of assessing this
question is .....
The most extreme cases always happen where the track crosses a cell boundary
(>~ 1 microsec - max drift time difference between hit arrival times).
To account for this possibility, it is proposed to have at least two
- Determine how far into the shift register to place the pivot element.
This is defined as the point where no valid masks are lost because one
of the hits has not yet clocked onto the register.
- With the pivot element position decided, next work out how long
the registers have to be. - This is defined as the length at which no valid
masks are lost due to the earliest arriving hits clocking off the register.
Most Urgent Questions
A very important deadline is approaching!
By the end of April, we are asked
to demonstrate to the DESY PRC that the track segment finding can be done
inside the available 2 microsecs.
First attempts at Quartus simulations are thus needed quickly! The first
aim should just be to get a feel for the number of cycles required for each
operation. We are asked
to report at the meeting on April 5th.
The following open questions remain to be answered (among many others). ....
- Interfaces with L2 (VME?) -
Adam, Dave, Scott to discuss with SCS?
- Should we use the e-vision readout chip?
- How are we going to read this thing out?
- How do we plan to calibrate the CJC and how
often does this need to be updated?
- Should data transmission to L1 trigger / L2
be encoded / unencoded / LVDS / optical?...
Video conference DESY - RAL, including plans to answer
PRC breakpoint - demonstrate L1 segment finding can be done in time.
Full level 1 meeting (Birmingham)
Compiled by P. Newman, 27/3/00