Mangled minutes of hardware meeting at RAL on 17th January 2001.
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Dave Sankey
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Dave had managed to pick a meeting room that proved intriguing for 
everyone to find (even the receptionist at the door didn't know where 
it was!).

Attendees:

Scott, Mohammed, Adam, Dave, Saeed, Darren Ballard (in part)

There was discussion on the VME schematic, in particular availability 
and ordering of components (namely that RAL would order whatever 
components it needed).

As it had been given to SCS as final the back-plane connector pin-out 
was now final.

With regards to the VME interface there would be 10K pull-ups on the 
geographic addressing.  The parts list would be put on the web 
<http://www.hep.man.ac.uk/~scott/projects/h1/ftt/vme/vmecomponents.html>. 
The bus LVDS clock (STC and HClk) need minimum stubs.

The primary data link is not yet defined, with the timetable for 
fixing this being needed the first week in April.

The VME clock would be at 20 MHz, up from the original 16 MHz, with 
the actual VME at 10 MHz.

With regard to the analogue connections on the analogue buffer card, 
signal quality would take precedence over most natural wire ordering. 
On the FEM it was noted that the ADC needs two clocks, one 180 
degrees out of phase, to do the offset sampling that is proposed 
(note added by Dave after meeting, this offset clocking now looks 
like a red herring, as difference in cable length on-detector is 
compensated in the main by different length cables from CDA to 
rucksack).

On the FEM time scales, the critical bottleneck is the Drawing 
Office, as we only have Darren.  Given that the current time scale 
didn't give a fully working FEM in time for the June cosmics we 
decided on a revised target of assembled boards running in FADC mode 
for the cosmic run as the minimum that would be acceptable, paying to 
accelerate production of the boards.  It was noted that the analogue 
cables would be required in good time for this from Andre'.

On the FEM back-plane we decided that the STC signals required were 
pipeline-enable, L1Keep, L3Kepp (for R/O) and what I've written as 
programmed I/O.

There was then lengthy discussion on the DC signal offset levels 
going into the ADC, as Adam's default levels would waste the most 
significant bit in the ADC.

Dave said that he was not happy with this.  Scott said that he 
couldn't cope with providing the DC bias.  Adam was reluctant but 
finally gave in and will shift the offset before going into the ADC 
(as an aside, we noted that Analog Devices now have a preliminary 
spec sheet for Andre's favourite, a 10 bit version of the ADC that we 
want).  The gain into the ADC should be such that the ADC saturates 
at half full scale into the existing F1001 system.

Finally specification should be signed off by end of the month.